1. Field
One or more embodiments of the present invention relate to the field of semiconductor devices and more particularly to a transistor with enhanced reduced surface field (RESURF) effect.
2. Discussion of Related Art
Power semiconductor devices, such as high voltage transistors, are designed to support high voltage levels in various applications. In one instance, high voltage transistors are implemented in the peripheral circuitry of semiconductor memory devices such as Flash memory devices. There is constant desire to reduce the size of these memory devices, including the memory cells and the peripheral devices to improve performance. However, downscaling of high voltage transistors is limited by several factors. For example, to maintain a high drain-source breakdown voltage (BVdss), the contact to gate spacing must remain relatively large. Furthermore, the transistor must supply the drive current demanded by circuit operation, which translates to a large on-resistance (Ron), thus resulting in a wide device.
One method of reducing the size of the transistor is by increasing the BVdss-Ron ratio. A technique known as reduced-surface-field (RESURF) effect has been used to design transistors with high BVdss and low Ron. FIG. 1A illustrates a top plan view of a high voltage transistor known in the art that implements the dielectric RESURF concept. The high voltage transistor 10 comprises a substrate 20 having a source region 31 and a drain region 32. A plurality of shallow trench isolation (STI) regions 40 interleave the drain extensions 33 of the drain region 32 to induce a doping dilution in the drain extensions 33. A poly gate 50 is formed between the source and drain regions 31, 32, where the poly gate 50 comprises multiple poly gate fingers 51 formed on top of the STI regions 40. FIG. 1B shows the cross-sectional view of the poly gate fingers 51 formed on the STI regions 40. The poly gate fingers 51 induce a capacitive coupling with the STI regions 40, which enhances the depletion of the drain extensions 33. As a result, the electrical field is more evenly distributed over the drain extensions 33, thus inducing a higher breakdown voltage (BVdss).
The high voltage transistor 10 shown in FIGS. 1A and 1B is formed by a single poly gate 50. However, there are difficulties in integrating the high voltage transistor 10 in a typical Flash (NAND) memory fabrication process that forms a double poly layer gate stack, where the lower poly gate is self-aligned to the active area. Hence, there is need for an improved method of fabricating a transistor with the dielectric RESURF effect.